(1) Field of the Invention
The invention relates to a method of planarizing an integrated circuit device, and more particularly, to a method of planarizing a submicron integrated circuit device using spin-on-glass wherein the spin-on-glass layer is thermally cured and then ion implanted to improve the outgassing characteristics of the layer.
(2) Description of the Prior Art
In conventional planarization of the metallurgy-dielectric layers of an integrated circuit, a metal is deposited and patterned by conventional lithography and etching techniques. Then the dielectric layer, which is typically silicon oxide material, is formed thereover. The dielectric layer may now be etched back to planarize the metallurgy-dielectric layers. There are basic problems in the choice of thickness of the dielectric layer. The problems occur particularly where there are substantially different heights on the surfaces of the integrated circuit, particularly in the formation of memory word lines and the like in memory products. For example, in the areas where contact is planned to be made to the patterned metal, it is desired to have a thick dielectric layer to keep planarity, but the thick dielectric will cause voids in other areas. Alternatively, if a thin dielectric layer is used, there is lost planarity in the contact area and etchback encroachment of the metal pattern, but there will not be a void problem in other surface areas of the integrated circuit. There is not a good solution for this planarity versus void surface problem in the art.
The spin-on-glass materials have been used for planarization of integrated circuits. The material to be applied is thoroughly mixed in a suitable solvent. The spin-on-glass material suspended in the vehicle or solvent is deposited onto the semiconductor wafer surface and uniformly spread thereover by the action of spinning the wafer. The material fills the indentations in the integrated circuit wafer surface, that is planarization. Most of the vehicle or solvent is driven off by a low temperature baking step often followed by vacuum degassing. Other coatings of the spin-on-glass material are applied, baked and vacuum degassed until the desired spin-on-glass layer is formed.
The final step in the making of the spin-on-glass layer is curing. Curing is a high temperature heating step to cause the breakdown of the silicate or siloxane material to a silicon dioxide like cross linked material.
In the conventional sandwich process, a conformal oxide is first deposited followed by a coating of spin-on-glass material. This is cured at about 425.degree. C. to become a silicon dioxide layer with some other materials, such as organics depending upon the particular spin-on-glass material that is used. The final oxide of the sandwich is deposited.
In general, there are two kinds of spin-on-glass planarization. One uses etchback and the other does not use etchback. The etchback process uses an etching back step to remove the spin-on-glass layer which will exist in the via holes. Its advantage is to protect the via hole from moisture or other gases absorbed in the cured spin-on-glass which may damage the via stepcoverage or metallurgy. The disadvantages for this etchback process are (1) this process needs an extra etchback step and (2) it is difficult to keep the etching selectivity of spin-on-glass to silicon oxide so that there could be produced a poorer planarization that expected. With the non-etchback process, it is easy to cause a poisoned via. During the deposition of the metallurgy, moisture and other gases can be released from the spin-on-glass layer in its sidewall regions to react with the metallurgy to cause the so-called poisoned via. This will cause poor metal stepcoverage or even an metallurgy and electrical open in the via.
A number of patents have addressed these and other problems in spin-on-glass planarization. U.S. Pat. No. 5,003,062 to Yen involves a sandwich process in which the spin-on-glass material can be either silicate or siloxane. A vacuum degassing step is used. In U.S. Pat. No. 4,775,550 to Chu et al, the first insulating layer is very thick, on the order of 8000 to 10,000 Angstroms. This thickness causes voids in the submicron area. The aforementioned patent to Chu et al as well as U.S. Pat. Nos. 4,676,867 to Elkins et al and 4,885,262 to Ting et al each show spin-on-glass etchback processes with use of a sandwich dielectric.
The Joe H. K. Leong U.S. Pat. No. 5,192,697 describes an alternative curing method to that of the thermal curing method. His method involves the use of ion implantation to cause heating within the spin-on-glass layer to cause curing of the layer. "Modification Effects in Ion-Implanted SiO.sub.2 Spin on Glass" by N. Moriya et al in J. Electrochem, Soc. Vol, No 5 May 1993, pp 1442-1449 describes the physical effects caused by ion implanting into silicate and siloxane spin-on-glass layers formed on silicon wafers.